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| author | Subrata Banik <subrata.banik@intel.com> | 2020-08-05 13:30:30 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-07 06:05:12 +0000 |
| commit | 45caf972ede1e3efcc56d2558cb27171cb8748b6 (patch) | |
| tree | 12f3fe50dd32f25b3360ea78ad51a92bd2db5363 /Documentation/mainboard/intel | |
| parent | ad3dceae303cacee3e836e918a26380c9bfe94a2 (diff) | |
soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to
programming PWRMBASE and enable BIT 2 after programming PWRMBASE
along with PCI_COMMAND_MEMORY (BIT 1).
Also perform below operations
1. Use pci_and_config16 instead of pci read and write
2. Use setbits32 instead of mmio read and write
Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'Documentation/mainboard/intel')
0 files changed, 0 insertions, 0 deletions