diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-06-15 11:49:16 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-13 10:41:50 +0000 |
| commit | 29f1866e9592bd3bc2d9ec25039a732bfa30b5fa (patch) | |
| tree | ee859ca0fe03050fee4c8abf187c90bb4fc9245f /Documentation/mainboard/intel | |
| parent | f916b3cd8e1c8cebd323f8f9bbaac423d740b3ae (diff) | |
soc/mediatek/mt8188: Enable mmu operation for L2C SRAM and DMA
- Turn off L2C SRAM and reconfigure as L2 cache:
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM:
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I10f1cb8c62dfa78f59a4a5ea6087609668a0c2aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65753
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/mainboard/intel')
0 files changed, 0 insertions, 0 deletions