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authorFelix Held <felix-coreboot@felixheld.de>2021-03-26 01:13:53 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-03-29 19:52:22 +0000
commit2421de6701565269d1e10845e487a588abb8fc40 (patch)
tree6e747070c58e4d92906c242d9dc21e48423282b6 /Documentation/mainboard/intel
parentdd737142490828c3aa2244216a2fda6df26a4c47 (diff)
soc/amd/cezanne: factor out UPD-M configuration from romstage
Move the parts of romstage.c that populate the UPD-M data structure to the newly created fsp_m_params.c file. Since platform_fsp_memory_init_params_cb gets called from the FSP driver and not directly from car_stage_entry the two code parts in romstage.c weren't directly interacting. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f7f5879ac318372042ff703ebbe584ce1c32c91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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