soc/intel/common: Define post codes

For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.

cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done.  This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.

All other post codes remain identical.

POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions