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| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-04-23 16:17:37 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-04-24 03:16:57 +0000 |
| commit | f9c9fa2df8077d323f7c45a4a3f19ae40282ff44 (patch) | |
| tree | 2d49dc6f2936f4e73d92a9754f6c4bbbffaa24b4 /Documentation/mainboard/index.md | |
| parent | 8725e5f639cb71f405005586e01d6efa0042dc4b (diff) | |
mb/google/sarien: Toggle SSD reset pin on DVT2
SSD reset pin had been added on DVT2, the power sequnence requires
toggle in boot stage.
BUG=b:130741066
TEST=Boot up with simulated DVT2 platform and confirm SSD can be
detected during warm reboot.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/mainboard/index.md')
0 files changed, 0 insertions, 0 deletions