Docs: Replace Recommonmark with MyST Parser

Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.

For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:

* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)

MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:

```{toctree}
:maxdepth: 1

Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```

Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.

The toctrees were converted to the MyST syntax using the following
command and Python script:

`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`

```
import re
import sys

in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()

with open(sys.argv[1], "w") as f:
    for line in lines:
        match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
        if match is not None:
            if not in_list:
                in_list = True
                f.write("```{toctree}\n")
                f.write(":maxdepth: 1\n\n")
            f.write(match.group(1) + " <" + match.group(2) + ">\n")
        else:
            if in_list:
                f.write("```\n")
            f.write(line)
            in_list = False

    if in_list:
        f.write("```\n")
```

While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.

This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.

Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.

These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`

Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.

From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.

TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.

[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html

Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 12 insertions, 12 deletions

diff --git a/Documentation/mainboard/hp/2170p.md b/Documentation/mainboard/hp/2170p.md
index 5f67c38b11..6b8060e195 100644
--- a/Documentation/mainboard/hp/2170p.md
+++ b/Documentation/mainboard/hp/2170p.md
@@ -74,7 +74,7 @@ The EHCI debug port is the left USB3 port.
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+--------------------------------------------------+
 | CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
 +------------------+--------------------------------------------------+
diff --git a/Documentation/mainboard/hp/2560p.md b/Documentation/mainboard/hp/2560p.md
index 65a87d1068..4565171c0e 100644
--- a/Documentation/mainboard/hp/2560p.md
+++ b/Documentation/mainboard/hp/2560p.md
@@ -80,7 +80,7 @@ Schematic of this laptop can be found on [Lab One].
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+--------------------------------------------------+
 | CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
 +------------------+--------------------------------------------------+
diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md
index 857a1d9558..9646ba9163 100644
--- a/Documentation/mainboard/hp/8760w.md
+++ b/Documentation/mainboard/hp/8760w.md
@@ -7,7 +7,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.
 
 ## Flashing coreboot
 
-```eval_rst
+```{eval-rst}
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -66,7 +66,7 @@ clip to read and flash the chip.
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+
diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md
index 72df9e3e02..f0783975dd 100644
--- a/Documentation/mainboard/hp/compaq_8200_sff.md
+++ b/Documentation/mainboard/hp/compaq_8200_sff.md
@@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
 
 ## Flashing coreboot
 
-```eval_rst
+```{eval-rst}
 +---------------------+-------------------------+
 | Type                | Value                   |
 +=====================+=========================+
@@ -128,7 +128,7 @@ as otherwise there's not enough space near the flash.
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+
diff --git a/Documentation/mainboard/hp/compaq_8300_usdt.md b/Documentation/mainboard/hp/compaq_8300_usdt.md
index c2800b3f3f..4c2989a3a5 100644
--- a/Documentation/mainboard/hp/compaq_8300_usdt.md
+++ b/Documentation/mainboard/hp/compaq_8300_usdt.md
@@ -5,7 +5,7 @@ from [HP].
 
 ## Flashing coreboot
 
-```eval_rst
+```{eval-rst}
 +---------------------+-------------+
 | Type                | Value       |
 +=====================+=============+
@@ -42,7 +42,7 @@ Wake on LAN is active works great.
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+
diff --git a/Documentation/mainboard/hp/elitebook_820_g2.md b/Documentation/mainboard/hp/elitebook_820_g2.md
index 5d35c30211..6fafbe1758 100644
--- a/Documentation/mainboard/hp/elitebook_820_g2.md
+++ b/Documentation/mainboard/hp/elitebook_820_g2.md
@@ -124,7 +124,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+-----------------------------+
 | SoC              | Intel Broadwell             |
 +------------------+-----------------------------+
diff --git a/Documentation/mainboard/hp/folio_9480m.md b/Documentation/mainboard/hp/folio_9480m.md
index 0fededfda4..912bf93664 100644
--- a/Documentation/mainboard/hp/folio_9480m.md
+++ b/Documentation/mainboard/hp/folio_9480m.md
@@ -138,7 +138,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+-----------------------------+
 | CPU              | Intel Haswell-ULT           |
 +------------------+-----------------------------+
diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md
index 11676208ac..303b59aecf 100644
--- a/Documentation/mainboard/hp/z220_sff.md
+++ b/Documentation/mainboard/hp/z220_sff.md
@@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
 
 ## Flashing coreboot
 
-```eval_rst
+```{eval-rst}
 +---------------------+-------------+
 | Type                | Value       |
 +=====================+=============+
@@ -58,7 +58,7 @@ even interchangeable, so should do coreboot images built for them.
 
 ## Technology
 
-```eval_rst
+```{eval-rst}
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+