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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-08 11:00:08 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-09 18:45:00 +0000
commit659a591aa70e2df86c4ec576b8015ac78cd1ef03 (patch)
tree45777474d077351e767733cfbf1199e95a7aa01e /Documentation/lib/timestamp.md
parent6545145f0d3cda84c0dc8a01db6ce03f6dd87832 (diff)
mb/google/brya: Reorganize flashmap
Intel ADL-P supports an additional memory-mapped 16MiB window into the platform SPI flash. Support for this window already exists at the SoC level, so all that is needed is to properly organize the flash map to take advantage of this. FW_SECTION_A moves down to the bottom of the available space in the lower 16MiB half, and FW_SECTION_B moves to the bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M. BUG=b:182088676 TEST=build and boot to OS from FW_MAIN_A Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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