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authorShaunak Saha <shaunak.saha@intel.com>2016-06-10 19:36:49 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-12 20:38:56 +0200
commit6e5c5a15bc9fe709943598ede0eb52f9766cbb02 (patch)
tree13f077c46160490697b9882d36fb5c29951d8516 /Documentation/hypertransport.svg
parent7f149c7bb4744459c775c32c71fe222c792cea19 (diff)
intel/amenia: Add GPE routing settings
This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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