diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2021-05-10 14:59:25 -0700 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2021-05-16 22:17:52 +0000 |
| commit | 64b1352d05cfb0ddda25673cf88938761e9974db (patch) | |
| tree | 172bb6085fa5ee3262a75834f9febed66337084d /Documentation/getting_started/writing_documentation.md | |
| parent | c4813ea2604600476fa3c95557135b3225f404aa (diff) | |
soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards
DisableDimmMc0Ch0 upds changed to DisableMc0Ch0 in new FSP releases. The definition
of the upd also changed. Changed FSP meminit code to work based on new definition of the UPDs.
Before:
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
After:
0:Enable, 1:Disable
TEST=Boot to OS
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54036
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/getting_started/writing_documentation.md')
0 files changed, 0 insertions, 0 deletions