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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-06-06 15:45:51 +0200
committerFelix Held <felix-coreboot@felixheld.de>2019-06-21 12:53:44 +0000
commitffbc3b5f5fb0bdf57b6d5e3808e55e761241d8ba (patch)
tree3b93fdcfa5c19389535833cba6478becc6f0dce1 /Documentation/drivers
parentc469712166257da7b159773b42f067090b63e34e (diff)
drivers/ipmi: Add chip ops
* Add chips ops for IPMI KCS. * Get IPMI version over KCS. * Generates ACPI SPMI table for IPMI KCS. * Generates SMBIOS type 38 for IPMI KCS. * Generates ACPI SPMI device for IPMI KCS on LPC device. * Add documentation To use this driver on BMC that support KCS on I/O: 1. Add an entry to the devicetree.cb: chip drivers/ipmi device pnp ca2.0 on end # IPMI KCS end 2. Select IPMI_KCS in Kconfig. 3. (Optional) enable LPC I/O decode for the given address. Tested on Wedge100s. Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'Documentation/drivers')
-rw-r--r--Documentation/drivers/index.md7
-rw-r--r--Documentation/drivers/ipmi_kcs.md47
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diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
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+# Platform indenpendend drivers documentation
+
+The drivers can be found in `src/drivers`. They are intended for onboard
+and plugin devices, significantly reducing integration complexity and
+they allow to easily reuse existing code accross platforms.
+
+* [IPMI KCS](ipmi_kcs.md)
diff --git a/Documentation/drivers/ipmi_kcs.md b/Documentation/drivers/ipmi_kcs.md
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+# IPMI KCS driver
+
+The driver can be found in `src/drivers/ipmi/`. It works with BMC that provide
+a KCS I/O interface as specified in the [IPMI] standard.
+
+The driver detects the IPMI version, reserves the I/O space in coreboot's
+resource allocator and writes the required ACPI and SMBIOS tables.
+
+## For developers
+
+To use the driver, select the `IPMI_KCS` Kconfig and add the following PNP
+device under the LPC bridge device (in example for the KCS at 0xca2):
+
+```
+ chip drivers/ipmi
+ device pnp ca2.0 on end # IPMI KCS
+ end
+```
+
+**Note:** The I/O base address needs to be aligned to 2.
+
+The following registers can be set:
+
+* `have_nv_storage`
+ * Boolean
+ * If true `nv_storage_device_address` will be added to SMBIOS type 38.
+* `nv_storage_device_address`
+ * Integer
+ * The NV storage address as defined in SMBIOS spec for type 38.
+* `bmc_i2c_address`
+ * Integer
+ * The i2c address of the BMC. zero if not applicable.
+* `have_apic`
+ * Boolean
+ * If true the `apic_interrupt` will be added to SPMI table.
+* `apic_interrupt`
+ * Integer
+ * The APIC interrupt used to notify about a change on the KCS.
+* `have_gpe`
+ * Boolean
+ * If true the `gpe_interrupt` will be added to SPMI table.
+* `gpe_interrupt`
+ * Integer
+ * The bit in GPE (SCI) used to notify about a change on the KCS.
+
+
+[IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf