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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 17:39:44 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-17 15:11:41 +0000 |
| commit | e33c50d74c518e0ebe1f2d8e88cebd023bb94bcf (patch) | |
| tree | eb9f077c7b8e9e9c0b09a70d9bebcc4ab940a840 /Documentation/conf.py | |
| parent | e9649218bf69fee503fe7ce7b562004bab8781bf (diff) | |
cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZE
AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the
romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol.
Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'Documentation/conf.py')
0 files changed, 0 insertions, 0 deletions