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authorAnil Kumar <anil.kumar.k@intel.com>2020-07-30 14:31:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-17 06:41:10 +0000
commitf4fa906270623125316f1203766d693adda43739 (patch)
treea37af732dd6e799845eb5860e892c8afa8950650 /Documentation/community/services.md
parent5b40682313c24dd35ac866c191657b3c24e6ae30 (diff)
mb/tglrvp: Update SPD files for Hynix
- Increase DDR Frquency limit to support data rate 4266 Mbps Bug=None Test=Build and boot on tglrvp hardware; $dmidecode --type 17 reflects memory Speed = 4266 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44149 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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