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| author | Nick Vaccaro <nvaccaro@google.com> | 2020-04-06 14:42:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 09:50:41 +0000 |
| commit | ba41ee1f0a74cf6b0ed0c068b6560e60f7d760eb (patch) | |
| tree | ce9e9e0345391148d4918238b7325051ba0dcd8d /Documentation/coding_style.md | |
| parent | 5926fb5035aca828711f6b3edb1c4242bb547f7e (diff) | |
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599,
1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
columns)
2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
x16)
This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).
BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'Documentation/coding_style.md')
0 files changed, 0 insertions, 0 deletions