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authorNico Huber <nico.h@gmx.de>2016-01-09 23:27:16 +0100
committerMartin Roth <martinroth@google.com>2016-01-14 19:07:45 +0100
commitb851cc69d67a98dd4df43e4ac8b56b7533aa13b6 (patch)
treef9923b8e67a379253e0a71967b1ef8cccdbdaeef /Documentation/codeflow.svg
parentc3571da2633c6de4f856e8b8d700526573212894 (diff)
nb/intel/gm45: Backport configuration of panel power timings
Register settings are the same as on newer chips (compare sandy- bridge), just at different locations. Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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