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| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-10-14 05:29:09 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:24:32 +0000 |
| commit | 448ecc0e0660f111b3932368a950f18dae01f578 (patch) | |
| tree | ec7cbddc6613f1bee77663d44eda7eb17d912bfb /Documentation/beginverbatim.tex | |
| parent | 3c6ad8d1843d63c37c8f413263fd140fa78f866a (diff) | |
soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG
base and size) to remaining SoCs.
Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'Documentation/beginverbatim.tex')
0 files changed, 0 insertions, 0 deletions