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authorPatrick Rudolph <siro@das-labor.org>2019-09-29 11:08:33 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-08 07:28:32 +0000
commit03a79520d6f62072ff3de75cc8bbbf0ff4876f62 (patch)
treea5e64772b790c563e25dd872a48f2cbbcdf4192d /Documentation/arch
parentd5321bf2fb6ddbceea21e8b8e38ae89288fcfb1a (diff)
cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler. x86_32 isn't affected by this change. As the rsm instruction used to leave SMM doesn't restore MSR registers, drop back to protected mode after running the smi_handler and restore IA32_EFER MSR (which enables long mode support) to previous value. NOTE: This commit does NOT introduce a new security model. It uses the same page tables as the remaining firmware does. This can be a security risk if someone is able to manipulate the page tables stored in ROM at runtime. USE FOR TESTING ONLY! Tested on Qemu Q35. Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/arch')
-rw-r--r--Documentation/arch/x86/index.md1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index 30dcc10e91..f5546d18d5 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -45,6 +45,7 @@ At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
* Add x86_64 exception handlers - *DONE*
* Setup page tables for long mode - *DONE*
* Add assembly code for long mode - *DONE*
+* Add assembly code for SMM - *DONE*
* Add assembly code for postcar stage - *TODO*
* Add assembly code to return to protected mode - *TODO*
* Implement reference code for mainboard `emulation/qemu-q35` - *TODO*