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authorPaul Menzel <pmenzel@molgen.mpg.de>2019-06-24 18:39:43 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-19 07:06:59 +0000
commitb9a5152cfab79ebdc539bc467a743c4198870747 (patch)
tree5011ceb4b8fadee88e488d4e1114f20b200127a9 /Documentation/arch/x86
parent5c2d1906d928f9ff388779a0a21141daea5d19e3 (diff)
Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/arch/x86')
-rw-r--r--Documentation/arch/x86/index.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index 11d8a4f77b..d22d31de1a 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -19,7 +19,7 @@ In order to add support for x86_64 the following assumptions were made:
* x86 payloads are loaded below 4GiB in physical memory and are jumped
to in *protected mode*
-## Assuptions for all stages using the reference implementation
+## Assumptions for all stages using the reference implementation
* 0-4GiB are identity mapped using 2MiB-pages as WB
* Memory above 4GiB isn't accessible
* page tables reside in memory mapped ROM