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| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-04-01 16:13:18 -0400 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-07-20 22:22:14 +0000 |
| commit | 65f558f576ac716b0639d8d18834b776a2a9f90b (patch) | |
| tree | 0ff64e25ac0f648565df5df5b1d7efbb1cb136a6 /Documentation/arch/riscv | |
| parent | 6a0e47019733890307d93329de79fc58f71ced77 (diff) | |
soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write
The SPI_RESTRICTED_CMD register is not a PCI configuration register. It
is memory mapped from the SPI bar.
Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50
TEST=Compile tested only
Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions