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| author | Subrata Banik <subrata.banik@intel.com> | 2019-05-15 20:08:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-05-16 04:35:00 +0000 |
| commit | 48b6be81a5753779f036818a62dd9d61c6abc9c0 (patch) | |
| tree | 662dad372019c64dc040ddde5f8d55004d27787a /Documentation/arch/riscv | |
| parent | dce10f8f92c4e771cf54544679fcbe10f094afdf (diff) | |
Remove remaining unnecessary ENV_RAMSTAGE guard
TEST=Able to build coreboot for CML.
Change-Id: I8a6a97d59277ebfc498c83bb039436ed7c89d2cd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions