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| author | Martin Roth <martinroth@chromium.org> | 2019-05-11 12:51:44 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-13 09:26:45 +0000 |
| commit | 2f0bbbfe9f3b3d68d75eabd35280fe8aaa9d8619 (patch) | |
| tree | cc0a9dbd1088ba17748dd6f1b1e920d96629d44b /Documentation/arch/riscv | |
| parent | ef9e85bbfdb24d228f1e6c37d916025c5d06ea53 (diff) | |
mb/lenovo/s230u: Rewrite trigger inversion ACPI code
The GPIO invert registers are already defined in the PCH code, so
just use the 8-bit versions of the registers instead of creating
a new GPIO field for the single bits.
This allows us to get rid of the Field(GPIO...) code that's causing
problems with IASL version 20190509.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions