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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-05-05 22:28:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-08 13:03:22 +0000 |
| commit | c6a9f506b75e097189e48732cce14e0842a4c086 (patch) | |
| tree | 38199fa2f55e2a1eab852354d1ac1fafb56ebd9d /Documentation/arch/riscv | |
| parent | dbfb6b92654f1fbc8799c46f142e31deea73fd9d (diff) | |
nb/amd/pi/00730f01/acpi/northbridge: don't hide PCI0 root device from OS
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
back from Stoneyridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e724292431be7f7c2a0b6678b426831e3c19154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74990
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions