diff options
| author | Keith Short <keithshort@chromium.org> | 2019-05-10 11:14:31 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-22 17:45:11 +0000 |
| commit | c58e3bd90a96bf01859d1c0af83926b1e17edff5 (patch) | |
| tree | 15eb21e5c0f6c9402b9d9fb11b4e85907528da24 /Documentation/POSTCODES | |
| parent | 15588b03b36aa875e2a2a31cc649a2d9dff7581e (diff) | |
post_code: add post code for video initialization failure
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'Documentation/POSTCODES')
| -rw-r--r-- | Documentation/POSTCODES | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index a9d392a9b0..0e67dd173c 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -21,6 +21,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized 0xe4 Critical hardware component could not initialize +0xe5 Video subsystem failed to initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload |