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authorKeith Short <keithshort@chromium.org>2019-05-16 14:08:31 -0600
committerMartin Roth <martinroth@google.com>2019-05-22 16:54:46 +0000
commit24302633a558e545efcc84178136bd1879f6d8ee (patch)
treed1ae419a5796ffb570b9862e60884b2b9d975c1b /Documentation/POSTCODES
parentbb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee (diff)
post_code: add post code for memory error
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails to initialize RAM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'Documentation/POSTCODES')
-rw-r--r--Documentation/POSTCODES1
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diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
index 855940f433..2a8285b27f 100644
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@@ -19,6 +19,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
0xe0 Boot media (e.g. SPI ROM) is corrupt
0xe1 Resource stored within CBFS is corrupt
0xe2 Vendor binary (e.g. FSP) generated a fatal error
+0xe3 RAM could not be initialized
0xf8 Entry into elf boot
0xf3 Jumping to payload