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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-08-31 17:01:02 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-03 16:14:28 +0000 |
| commit | eaf87a9d6051eafcf4e4c315d9fa1844ab6ee45f (patch) | |
| tree | 110950d1ebc96d572bd66c8a6ded83cbc5a8a88c /Documentation/POSTCODES | |
| parent | dc0e066406d2ac36c83d4abd871f20e3121f7cc5 (diff) | |
soc/intel/alderlake: set power limits dynamically for thermal
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/POSTCODES')
0 files changed, 0 insertions, 0 deletions