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author | Sean Rhodes <sean@starlabs.systems> | 2021-04-30 16:38:17 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-22 14:47:05 +0000 |
commit | 69ed3ed5d8c944a90873c10e8ca3bc15042dda22 (patch) | |
tree | 07c00fa9f8aaf75e4b09911c421036435465b839 /Documentation/Makefile.sphinx | |
parent | 89b6d4bf12aed24f7988009f414435f76d098810 (diff) |
soc/intel: Allow enable/disable ME via CMOS
Add .enable method that will set the CSME state. The state is based on
the new CMOS option me_state, with values of 0 and 1. The method is very
stable when switching between different firmware platforms.
This method should not be used in combination with USE_ME_CLEANER.
State 1 will result in:
ME: Current Working State : 4
ME: Current Operation State : 1
ME: Current Operation Mode : 3
ME: Error Code : 2
State 0 will result in:
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 0
Tested on:
KBL-R: i7-8550u
CML: i3-10110u, i7-10710u
TGL: i3-1110G4, i7-1165G7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'Documentation/Makefile.sphinx')
0 files changed, 0 insertions, 0 deletions