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authorArthur Heymans <arthur@aheymans.xyz>2017-09-25 09:40:54 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-04-17 10:39:45 +0000
commitadc571a54c484bc5a4bb7785db8eda1be153eed9 (patch)
tree383e4a655a22bdcfa7012cacf01daccc63f219fe /Documentation/Lesson2.md
parent0cdaad36eb033eec831ad1eecec785ce89950ca7 (diff)
nb/intel/x4x: Use SPI flash to cache raminit results
Stores information obtained from decoding dimms and receive enable results for future use. Depreciates using rtc nvram to store receive enable settings. A notable change is that receive enable results are always reused, not just on a resume from S3. This requires cbmem to be initialized a bit earlier, right after the raminit finished to be able to add the sysinfo struct to cbmem which gets cached to the SPI flash in ramstage. TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in raminit goes from 133,857ms (using i2c block read to fetch SPD) to 21,071ms for cached results. Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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