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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-04-09 13:05:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-10 10:50:06 +0000 |
| commit | 8ee93ae26786c11f5169aedceb5b2670ff53568a (patch) | |
| tree | ead95aded2e49b14c8500f23a4f9ac87487da5dd /Documentation/Intel | |
| parent | 7fa9f73ac7b55272f15236a019f07c468b1f05c9 (diff) | |
Documentation: Fix a bunch of typos
Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/Intel')
| -rw-r--r-- | Documentation/Intel/NativeRaminit/SandyBridge_registers.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md index 2dce11bcc8..c96189088c 100644 --- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md +++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md @@ -966,7 +966,7 @@ Please handle with care ! *Width:* 24 Bit -*Desc:* TC_DBP - Timming of DDR - Bin Parameter Register, Channel 0 +*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0 |Bit| Description | |---|-------------| |