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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-06 13:25:09 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-08 16:43:53 +0200 |
| commit | 1d9370b3a58ddfcadda0692500e970109bcbb29f (patch) | |
| tree | 2ad94543d07dba585e222e0b310dec036db22219 /Documentation/Intel/fsp1_1.html | |
| parent | 49e917bffdb4d43caa418b9712235d174272a664 (diff) | |
nb/amd/mct_ddr3: Add MCE reporting logic
When a fatal error and subsequent sync flood / reset occurs,
the MCA status registers may contain valuable information on
the cause of the fatal error. Add functions to report MCEs and
reset the MCA status registers early in the boot process.
Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14265
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/fsp1_1.html')
0 files changed, 0 insertions, 0 deletions