diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-31 11:48:15 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-05 22:53:11 +0100 |
| commit | 7e0078b990b7b498391505fb5c492ff7ed8e54cb (patch) | |
| tree | c256d127efd4c6af26701addeda6aa67dad717c1 /Documentation/Intel/development.html | |
| parent | a1e4de47c6775acfc6ed692a8875e94db85a5834 (diff) | |
Documentation: Add the x86 FSP Binary
Document how to add the FSP binary to the SPI flash image.
TEST=None
Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13442
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/development.html')
| -rw-r--r-- | Documentation/Intel/development.html | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 68a52c8c98..2b23b39e23 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -70,9 +70,62 @@ <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> + <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> </ol> + +<hr> +<table border="1"> + <tr bgcolor="#c0ffc0"> + <th colspan=3><h1>Features</h1></th> + </tr> + <tr bgcolor="#c0ffc0"> + <th>SoC</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>Cache-as-RAM</td> + <td> + <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> + FSP binary: + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br> + Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a> + called from + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br> + Disable: FSP 1.1 TempRamExit called from + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> + </td> + <td>FindFSP: POST code 0x90 + (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) + is displayed<br> + Enable: POST code + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> + is displayed<br> + Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit + </td> + </tr> + <tr bgcolor="#c0ffc0"> + <th>FSP</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>TempRamInit</td> + <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td> + <td>FSP binary found: POST code 0x90 + (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) + is displayed<br> + TempRamInit successful: POST code + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> + is displayed<br> + </td> + </tr> +</table> + + + <hr> <p>Modified: 31 January 2016</p> </body> |