diff options
| author | Christian Walter <christian.walter@9elements.com> | 2020-05-23 15:54:43 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-06-02 09:39:19 +0000 |
| commit | 061cd78a1aba4a31ee61dc6f6bafc3a35537cf3e (patch) | |
| tree | a14c029aef936dd3028f21b911e56fc6d3102957 /Documentation/Intel/SoC | |
| parent | 1f572b9276ae3d20b37dbdb52e466ecfe5bbe06b (diff) | |
soc/intel/cannonlake: Add RP configuration settings
Add RP configuration settings like Advanced Error Reporting(AER),
Latency Tolerence Reporting (LTR), Max Payload and Active State Power
Management (ASPM).
Tested on CFL platform
Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/Intel/SoC')
0 files changed, 0 insertions, 0 deletions