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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-03-04 16:49:40 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-21 19:46:59 +0100 |
| commit | d75ed0bfd9238b210fdca136784cd699696421c7 (patch) | |
| tree | 403700be6619d403c68bbd866f5cdc47195fdfbf /Documentation/Intel/SoC/soc.html | |
| parent | 1f1f2c4d38dc5b58e0051f9d80086bc2a083a7cd (diff) | |
soc/intel/quark: Disable the ROM shadow
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing successful display of 0x000ffff0 - 0x000fffff does not match
the end of the SPI flash.
Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/SoC/soc.html')
0 files changed, 0 insertions, 0 deletions