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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-01-10 11:35:24 -0700 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-01-12 16:00:32 +0000 |
| commit | 0814b122281d2e4f10e40c2a8d5085f810e2730e (patch) | |
| tree | e20ce1ca7b9d83571bc13ba2b9d245500e788ed2 /Documentation/Intel/NativeRaminit | |
| parent | 533ea7adb5d23d32c854f4a3bdbf9c31df7299b4 (diff) | |
amd/stoneyridge: Keep SPI flash cacheable during POST
A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable. After MTRR
setup, reenable the setting for the duration of POST.
TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683
Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'Documentation/Intel/NativeRaminit')
0 files changed, 0 insertions, 0 deletions