diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-04-25 21:45:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-27 09:09:27 +0000 |
| commit | 0c80d2f8e30f79f0c35ae7de79855736297db1d7 (patch) | |
| tree | 793702a77b18d1574fd3dc7665741cecd8d98705 /Documentation/Intel/NativeRaminit/SandyBridge_registers.md | |
| parent | 4713b5cd9e2831adba5b5590c40c4d1a6aa1184f (diff) | |
Documentation/Intel/NativeRaminit: Remove trailing whitespace
Change-Id: I1d38aea07e2d9ffb89115410603a5beac5e4d44d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/Intel/NativeRaminit/SandyBridge_registers.md')
| -rw-r--r-- | Documentation/Intel/NativeRaminit/SandyBridge_registers.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md index 913d52e91b..bffbf76179 100644 --- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md +++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md @@ -2,7 +2,7 @@ The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device. -This documentation is incomplete and might be incorrect. +This documentation is incomplete and might be incorrect. Please handle with care ! **MCHBAR + 0x4** |