summaryrefslogtreecommitdiff
path: root/Documentation/Intel/Board
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-03-24 00:17:35 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-04-08 16:47:16 +0000
commitf8e440cadf4f332c676fddafd0357ecc07de5a4c (patch)
treeebfeb3f5e29049ae8bedd838f16207fd732b8694 /Documentation/Intel/Board
parentb640e22a419f3240d9dde582fe7464ddd52fbe4b (diff)
mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boards
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/Intel/Board')
0 files changed, 0 insertions, 0 deletions