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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-09-21 18:57:04 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-26 18:52:08 +0000
commitae91cdabf60b97d3205de3aa55954dd4f5903845 (patch)
tree8a559f6372a5dba9203709ce181efb5c3d7549b7 /Documentation/AMD-S3.txt
parentbdebc8918c4b19c2065d8fd9469cf507f13f3e36 (diff)
arch/riscv: Advance the PC after handling misaligned load/store
After emulating an instruction in the misaligned load/store handler, we need to increment the program counter by the size of instruction. Otherwise the same instruction is executed (and emulated) again and again. While were at it: Also return early in the unlikely case that the faulting instruction is not 16 or 32 bits long, and be more explicit about the return values of fetch_*bit_instruction. Tested by Philipp Hug, using the linuxcheck payload. Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling") Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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