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authorKane Chen <kane.chen@intel.com>2019-02-12 21:14:13 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-15 16:23:44 +0000
commit223ddc298a1a8e25a493987d84c629ed152821d1 (patch)
tree3dab78836d0483ad5e23709e142d258ba037002d /Documentation/AMD-S3.txt
parent1ac2ad0fbe8c1d7029e4f593fefe763212df6728 (diff)
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors. BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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