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authorShelley Chen <shchen@google.com>2019-02-06 15:21:55 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-21 11:31:19 +0000
commit3cce7a0311b85f22e3b653bee1bf1c0e4c7e4e45 (patch)
treeb61a1cf78fea666231248e1920abbda45e48ee04 /COPYING
parentd01a995cd3e1adfd5af28a980eedac1fee0dddc1 (diff)
soc/intel/cannonlake: Add field to identify single channel memory
Variants of Hatch need to accommodate single channel DDR. Also, removing const modifier as we'll need to set these fields incrementally now. For the single channel configuration, we set MemorySpdPtr10 to 0. For the dual channel configuration, we set MemorySpdPtr10 to MemorySpdPtr00. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31262 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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