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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-03-13 11:12:56 +0200
committerPatrick Georgi <pgeorgi@google.com>2017-04-27 10:23:03 +0200
commita2b7bd859a313db85632dd0d6d6e467c4a4f995d (patch)
treed5e6e41eba645facb6c9205b328917d65c789792 /COPYING
parentfb2f667da2091ce2194274f95c2d5db024d46e63 (diff)
i82801gx: Enable PCI-to-PCI bridge
Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. Since the LPC function claims the resources for IOAPIC, ROM and low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI configuration will not overlap those regions and does not hide the resources mentioned in the original comment. The bridge was disable in the following commit [1] commit a8e1168064b34b46494b58480411a11bc98340f6 Author: Stefan Reinauer <stepan@coresystems.de> Date: Wed Mar 11 14:54:18 2009 +0000 This patch contains some significant updates to the i82801gx component and will be required for a series of later patches. Roughly it contains: but unfortunately it was not noted which system this caused problems with. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6 Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/2706 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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