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authorLijian Zhao <lijian.zhao@intel.com>2017-09-28 16:11:53 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-03 20:24:08 +0000
commit747f05675ecf2d0fa4635c3b25e5726f7fe7d98d (patch)
tree6aeac014ecd5f475f56fe3a02e3db41c46b711a6 /COPYING
parentc1a49286092affa2ba39ceed51a09547fa60aa07 (diff)
soc/intel/cannonlake: Add northbridge dsdt table
Add ACPI dsdt table for northbridge, report proper resources in dsdt entries. TEST=Boot up into OS fine. Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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