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authorPhilip Chen <philipchen@google.com>2019-08-07 18:51:55 -0700
committerFurquan Shaikh <furquan@google.com>2019-08-16 04:27:55 +0000
commit4055cd8b039da00fb93ac611c236a493ebbb62e3 (patch)
tree854c53e0be36278efb63710e303f7228db42832a /COPYING
parentaa3c0a5fad146687cff7e71b0459fccdc37f11b3 (diff)
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some previous work for Skylake: cb58683ef5 soc/intel/skylake: Add support for mode-aware DPTF ...to common DPTF code so that we can support mode-aware DPTF for other Intel platforms. BUG=b:138702459 BRANCH=none TEST=Manually test on hatch: (1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE to hatch baseboard dptf.asl (2)Flash custom EC FW code which updates DPTF profile number when entering/exiting tablet mode (3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp updated when device mode is switched (tablet/clamshell) Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34785 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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