summaryrefslogtreecommitdiff
path: root/AUTHORS
diff options
context:
space:
mode:
authorWisley Chen <wisley.chen@quanta.corp-partner.google.com>2021-09-13 10:08:03 +0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-22 02:35:33 +0000
commit04613e9b942098af65768f63fef1b41e6597c50f (patch)
treee4a02667144d27aea9fb8b1d7b06bef6f0dc8b83 /AUTHORS
parent16ae682cb93764016c6b31ef3761c011733ad683 (diff)
mb/google/brya/var/redrix: Correct SSD power sequence
The current power sequencing for the SSD does not work in a non-serial enabled BIOS image. It appears that the FSP scans the PCIe RPs before the SSD has time to prepare itself for PCIe, so the FSP disables the RP and so depthcharge cannot find a boot disk. Changing the power sequence timing to enable power in bootblock and deassert reset in ramstage follows the SSD's power sequence and allows it to be discovered by the FSP so the RP does not get disabled. BUG=b:199714453 TEST=build, boot into SSD, and run reboot stress test. Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'AUTHORS')
0 files changed, 0 insertions, 0 deletions