diff options
| author | Rob Barnes <robbarnes@google.com> | 2020-09-01 10:28:36 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-09-03 21:28:13 +0000 |
| commit | b132bf5a87784a8a57677f43607095330be9f3a1 (patch) | |
| tree | ede0b74f02c6c44a0f8f06dc4bdade39c9d0dfbc /AUTHORS | |
| parent | 327f1058d2feaa022407128aa9dac55f408b714c (diff) | |
soc/amd/picasso: Set max_speed_mts and configured_speed_mts
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts
instead. This will result in SMBIOS type 17 displaying more accurate
speed information.
BUG=b:167218112
TEST=Boot ezkinil and observe dmidecode -t17
dmidecode -t17
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 4096 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 3200 MT/s
Manufacturer: Unknown (0)
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: MT40A512M16TB-062E:J
Rank: 1
Configured Memory Speed: 2400 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'AUTHORS')
0 files changed, 0 insertions, 0 deletions