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| author | Subrata Banik <subrata.banik@intel.com> | 2019-09-03 16:19:30 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-04 10:56:22 +0000 |
| commit | fb6ea0af4015ba7d0fef49af833d3b1c19796b38 (patch) | |
| tree | af869f960ecff43fcd6628dc993b521e52b6ceff | |
| parent | e78d140b1193f09d5510316d610283ee2f2c8b15 (diff) | |
Documentation/soc/intel/fsp: Add link for external FSP2.1 spec
Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 6269445ff3..cd7fe0b302 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -45,6 +45,8 @@ those are fixed. If possible a workaround is described here as well. * [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf) +* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786) + ## Additional Features in FSP 2.1 specification - [PPI](ppi/ppi.md) |