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authorFelix Singer <felixsinger@posteo.net>2021-05-03 02:33:15 +0200
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-08-12 21:42:36 +0000
commitf9d7dc7ed3de9383740295871c8adde66c688425 (patch)
tree543cfe5f5135c4c62901feab6c0b215376b03176
parentc8fc542e1b7828e86e2d4a5b6b743ce7a7d50665 (diff)
soc/intel/alderlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
-rw-r--r--src/soc/intel/alderlake/fsp_params.c16
1 files changed, 5 insertions, 11 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index cb4552d3fe..3accdbb408 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -401,17 +401,11 @@ static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* Chipset Lockdown */
- if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
- s_cfg->PchLockDownGlobalSmi = 0;
- s_cfg->PchLockDownBiosInterface = 0;
- s_cfg->PchUnlockGpioPads = 1;
- s_cfg->RtcMemoryLock = 0;
- } else {
- s_cfg->PchLockDownGlobalSmi = 1;
- s_cfg->PchLockDownBiosInterface = 1;
- s_cfg->PchUnlockGpioPads = 0;
- s_cfg->RtcMemoryLock = 1;
- }
+ const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
+ s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp;
+ s_cfg->PchLockDownBiosInterface = lockdown_by_fsp;
+ s_cfg->PchUnlockGpioPads = !lockdown_by_fsp;
+ s_cfg->RtcMemoryLock = lockdown_by_fsp;
/* coreboot will send EOP before loading payload */
s_cfg->EndOfPostMessage = EOP_DISABLE;