diff options
author | Rob Barnes <robbarnes@google.com> | 2021-06-07 08:55:14 -0600 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-09 15:10:34 +0000 |
commit | f892b85e18bfead6ed1f135e50ed4e9544553278 (patch) | |
tree | 4da60b66b8b32b2f226744ba675cedb0e816b742 | |
parent | eca3e6278abd37da60cd68bb3705ce1cc01d4f47 (diff) |
device/dram: Add LPDDR4 utilities
Add lpddr4.c utility file with lpddr4_speed_mhz_to_reported_mts.
Fill in lpddr4_speeds using JDEC 209-4C table 210.
LPDDR4 SPD decoding utilities are not included since there isn't
a present need.
BUG=b:184124605
TEST=Build and run on guybrush
Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r-- | src/device/dram/Makefile.inc | 4 | ||||
-rw-r--r-- | src/device/dram/lpddr4.c | 70 | ||||
-rw-r--r-- | src/include/device/dram/lpddr4.h | 20 |
3 files changed, 92 insertions, 2 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 69fcfa8844..b91b128f85 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1,3 +1,3 @@ -romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c +romstage-y += lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c -ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c spd.c +ramstage-y += lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c spd.c diff --git a/src/device/dram/lpddr4.c b/src/device/dram/lpddr4.c new file mode 100644 index 0000000000..5b829f7812 --- /dev/null +++ b/src/device/dram/lpddr4.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/dram/lpddr4.h> +#include <string.h> +#include <memory_info.h> +#include <smbios.h> +#include <types.h> + +enum lpddr4_speed_grade { + LPDDR4_1600, + LPDDR4_2400, + LPDDR4_3200, + LPDDR4_4266 +}; + +struct lpddr4_speed_attr { + uint32_t min_clock_mhz; // inclusive + uint32_t max_clock_mhz; // inclusive + uint32_t reported_mts; +}; + +/** + * LPDDR4 speed attributes derived from JEDEC 209-4C table 210 + * + * min_clock_mhz = Previous max_clock_mhz + 1 + * max_clock_mhz = 1000/min_tCk_avg(ns) + * reported_mts = Standard reported DDR4 speed in MT/s + * May be slightly less than the actual max MT/s + */ +static const struct lpddr4_speed_attr lpddr4_speeds[] = { + [LPDDR4_1600] = { + .min_clock_mhz = 10, + .max_clock_mhz = 800, + .reported_mts = 1600 + }, + [LPDDR4_2400] = { + .min_clock_mhz = 801, + .max_clock_mhz = 1200, + .reported_mts = 2400 + }, + [LPDDR4_3200] = { + .min_clock_mhz = 1201, + .max_clock_mhz = 1600, + .reported_mts = 3200 + }, + [LPDDR4_4266] = { + .min_clock_mhz = 1601, + .max_clock_mhz = 2137, + .reported_mts = 4266 + }, +}; + +/** + * Converts LPDDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t lpddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) +{ + for (enum lpddr4_speed_grade speed = 0; speed < ARRAY_SIZE(lpddr4_speeds); speed++) { + const struct lpddr4_speed_attr *speed_attr = &lpddr4_speeds[speed]; + if (speed_mhz >= speed_attr->min_clock_mhz && + speed_mhz <= speed_attr->max_clock_mhz) { + return speed_attr->reported_mts; + } + } + printk(BIOS_ERR, "ERROR: LPDDR4 speed of %d MHz is out of range", speed_mhz); + return 0; +} diff --git a/src/include/device/dram/lpddr4.h b/src/include/device/dram/lpddr4.h new file mode 100644 index 0000000000..59ddc337e4 --- /dev/null +++ b/src/include/device/dram/lpddr4.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DEVICE_DRAM_LPDDR4_H +#define DEVICE_DRAM_LPDDR4_H + +/** + * @file lpddr4.h + * + * \brief Utilities for decoding LPDDR4 info + */ + +#include <device/dram/common.h> +#include <types.h> + +/** + * Converts LPDDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t lpddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz); + +#endif /* DEVICE_DRAM_LPDDR4_H */ |