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authorStefan Reinauer <reinauer@chromium.org>2015-07-21 14:37:13 -0700
committerMartin Roth <martinroth@google.com>2016-01-07 17:39:13 +0100
commitf8532b16bec1743b0528a215c71f67c8845e2a0c (patch)
tree17bfa83295c8e5e5e6b6f3c84722c4d8400469ed
parent24ca41d074cac0d1274821a250696dc35227821a (diff)
f14: Increase AP stack to 8k on 64bit
This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/11025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/vendorcode/amd/agesa/f14/gcccar.inc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 2104c271cd..8f395ce0d6 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
+#ifdef __x86_64__
+CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
+#else
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
+#endif
APIC_BASE_ADDRESS = 0x0000001B
APIC_BSC = 8 /* Boot Strap Core */