diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-22 17:38:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-23 18:03:15 +0000 |
| commit | f66e781336e992f0791480bd710ef32b71d4ad52 (patch) | |
| tree | fdff43d6c94abc5026e7ac5cd87ab13d21c9b15d | |
| parent | a754aa6d29f2078cffac6559a9efca6f9ce862ac (diff) | |
soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fch
Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 58a5ce9165..0798e20c04 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -86,7 +86,7 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -static void sb_clk_output_48Mhz(void) +static void fch_clk_output_48Mhz(void) { u32 ctrl; const struct soc_amd_picasso_config *cfg = config_of_soc(); @@ -231,7 +231,7 @@ void fch_init(void *chip_info) gpp_clk_setup(); - sb_clk_output_48Mhz(); + fch_clk_output_48Mhz(); sb_rfmux_config_override(); } |