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authorMartin Roth <gaumless@gmail.com>2023-08-04 12:24:24 -0600
committerMartin L Roth <gaumless@gmail.com>2023-08-14 15:14:45 +0000
commitf362bbd5c7ce5d96f4bed3adee9a8f3ccc2728e8 (patch)
treefb7b7d825286201c1888eb3643caf7198405f944
parent9802f1ee546478eec5dd94817ec9b0070e7ae23d (diff)
commonlib,console,nb,sb,security: Add SPDX licenses to Makefiles
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the commonlib, console, northbridge, security, and southbridge directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
-rw-r--r--src/commonlib/Makefile.inc2
-rw-r--r--src/console/Makefile.inc2
-rw-r--r--src/device/dram/Makefile.inc1
-rw-r--r--src/northbridge/intel/e7505/Makefile.inc2
-rw-r--r--src/security/Makefile.inc2
-rw-r--r--src/security/intel/Makefile.inc2
-rw-r--r--src/security/intel/cbnt/Makefile.inc2
-rw-r--r--src/security/intel/stm/Makefile.inc1
-rw-r--r--src/security/intel/txt/Makefile.inc2
-rw-r--r--src/security/memory/Makefile.inc2
-rw-r--r--src/security/tpm/Makefile.inc2
-rw-r--r--src/security/tpm/tss/vendor/cr50/Makefile.inc2
-rw-r--r--src/southbridge/amd/common/Makefile.inc2
-rw-r--r--src/southbridge/intel/i82870/Makefile.inc2
-rw-r--r--src/southbridge/ricoh/rl5c476/Makefile.inc2
-rw-r--r--src/southbridge/ti/pci1x2x/Makefile.inc2
16 files changed, 30 insertions, 0 deletions
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index e90ed4f283..86e8c5695c 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
subdirs-y += storage
bootblock-y += mem_pool.c
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4296426a05..fd98cf7354 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ramstage-y += vtxprintf.c printk.c vsprintf.c
ramstage-y += init.c console.c
ramstage-y += post.c
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index fc472ea711..eb2e629991 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1,3 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
romstage-y += ddr_common.c
ramstage-y += ddr_common.c spd.c
diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc
index 29ac4379cf..44a056b788 100644
--- a/src/northbridge/intel/e7505/Makefile.inc
+++ b/src/northbridge/intel/e7505/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
ramstage-y += northbridge.c
diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc
index 72b87dbe73..b7922d41d5 100644
--- a/src/security/Makefile.inc
+++ b/src/security/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
subdirs-y += vboot
subdirs-y += tpm
subdirs-y += memory
diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc
index 20aea273e0..25e28ed869 100644
--- a/src/security/intel/Makefile.inc
+++ b/src/security/intel/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
subdirs-y += txt
subdirs-y += stm
subdirs-y += cbnt
diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc
index 4c585b8664..e166634351 100644
--- a/src/security/intel/cbnt/Makefile.inc
+++ b/src/security/intel/cbnt/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)
all-y += logging.c
diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc
index d4da605bd7..90b7c188f7 100644
--- a/src/security/intel/stm/Makefile.inc
+++ b/src/security/intel/stm/Makefile.inc
@@ -1,3 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
# put the stm where it can be found
diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc
index e19bacfbf5..c1fc0c4527 100644
--- a/src/security/intel/txt/Makefile.inc
+++ b/src/security/intel/txt/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
romstage-$(CONFIG_INTEL_TXT_LIB) += txtlib.c
ifeq ($(CONFIG_INTEL_TXT),y)
diff --git a/src/security/memory/Makefile.inc b/src/security/memory/Makefile.inc
index 0882ca3660..4f07bbbcb4 100644
--- a/src/security/memory/Makefile.inc
+++ b/src/security/memory/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc
index ae06cb0ea6..ade9656940 100644
--- a/src/security/tpm/Makefile.inc
+++ b/src/security/tpm/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
subdirs-$(CONFIG_TPM_GOOGLE) += tss/vendor/cr50
## TSS
diff --git a/src/security/tpm/tss/vendor/cr50/Makefile.inc b/src/security/tpm/tss/vendor/cr50/Makefile.inc
index 8bacafd023..0a16fa1978 100644
--- a/src/security/tpm/tss/vendor/cr50/Makefile.inc
+++ b/src/security/tpm/tss/vendor/cr50/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ramstage-y += cr50.c
romstage-y += cr50.c
postcar-y += cr50.c
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
index e086dc3a20..ce8b3d41b5 100644
--- a/src/southbridge/amd/common/Makefile.inc
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -1 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
index d6ae171926..83ebca5af2 100644
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ b/src/southbridge/intel/i82870/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
ramstage-y += ioapic.c
diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc
index 3fa232f1f8..24e84d24e7 100644
--- a/src/southbridge/ricoh/rl5c476/Makefile.inc
+++ b/src/southbridge/ricoh/rl5c476/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y)
ramstage-y += rl5c476.c
diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc
index 4f2a3d3ec9..05e57add48 100644
--- a/src/southbridge/ti/pci1x2x/Makefile.inc
+++ b/src/southbridge/ti/pci1x2x/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y)
ramstage-y += pci1x2x.c