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authorMario Scheithauer <mario.scheithauer@siemens.com>2023-05-22 14:44:27 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-01 15:41:22 +0000
commitf165bbdcf043dd9753c3b3a8e4ae86b0bfcd78ee (patch)
treef99bbe11deb064a409ae7e74398a3248827c1be6
parent385f4bb965cd0f67958d77389d5185a38cb3c9d8 (diff)
soc/intel/apollolake: Make SATA speed limit configurable
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SpeedLimit' allows to set the speed limit. It should be noted that Gen 3 equals the default value '0'. This means that inside FSP the same code is executed. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/apollolake/chip.c1
-rw-r--r--src/soc/intel/apollolake/chip.h10
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index e7a8168c94..bd40595ea3 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -736,6 +736,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* SATA config */
if (is_devfn_enabled(PCH_DEVFN_SATA)) {
silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport);
+ silconfig->SpeedLimit = cfg->sata_speed;
memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable,
sizeof(silconfig->SataPortsEnable));
}
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index a92d98218c..3951880610 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -25,6 +25,13 @@ enum pnp_settings {
PNP_PERF_POWER,
};
+enum sata_speed_limit {
+ SATA_DEFAULT = 0,
+ SATA_GEN1,
+ SATA_GEN2,
+ SATA_GEN3
+};
+
struct soc_intel_apollolake_config {
/* Common structure containing soc config data required by common code*/
@@ -215,6 +222,9 @@ struct soc_intel_apollolake_config {
/* Sata Power Optimisation */
uint8_t SataPwrOptimizeDisable;
+
+ /* SATA speed limit */
+ enum sata_speed_limit sata_speed;
};
typedef struct soc_intel_apollolake_config config_t;