diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-11-16 21:27:38 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-30 16:54:06 +0100 |
| commit | eedf6d8aa81e85b52d3c150dc992cbfb3077988d (patch) | |
| tree | 38867803b8488b7ecefb4732c8b576181ec7b9a4 | |
| parent | 1612cef81f20cb955d591f3cebcf864d784856ac (diff) | |
soc/intel/skylake: Disable Legacy PME for Root ports
Legacy PME are enabled by default in FSP UPD region.
When Legacy PME is enabled, then an SCI is generated and should be
handled by OS and BIOS/Coreboot in collboration. OS requires some
ACPI methods (eg _L69) which help to determine the wake source and also
to clear some registers. But this infrastructure is not present as of
now in coreboot and also linux handles PMEs natively.
Hence the SCI was never handled by OS and the status bits were never
cleared i.e., PCI_EXP_STS.
For this reason the level triggered SCI will remain active and the
system will wake up as soon as it enters S3.
To fix this, diabled Legacy PME (PmSci for Root ports).
Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17553
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f90f6bc096..59115a6b35 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); |